Electronic devices, particularly integrated circuits, include a large number of components fabricated by layering several different materials onto a silicon wafer. In order for the components to function as an electronic device, they are selectively, electrically connected to one another. For example, metal lines are utilized to provide component electrical connection within a layer, while vias connect different metallization and via layers.
When designing an electronic device, a designer creates a circuit description, including electrical connection of the components. The circuit description is input into a computer aided design (CAD) software package running on a computer to form a three-dimensional geometric image of the electronic device, known as a layout.
The layout program generates geometric data using the computer from which a semiconductor chip, circuit board, integrated circuit, or other electronic device is laid out and produced. Generally, a layout includes a set of geometric shapes contained in several layers. In a layout, metal lines are represented as trenches in a layer, and vias are represented as holes in a layer. Typically, the layout is checked to ensure that it meets all of the design requirements, e.g., that there are a sufficient number of vias between a particular upper metal line and a lower metal line to carry the requisite current between the metal lines. Subsequently, a mask that includes the semiconductor circuit layout pattern is imaged onto a substrate that is at least partially covered by a layer of resist using a lithographic projection.
However, there are many problems related to electronic device layouts. A difficult problem relating to via spacing and arrangement arises as electronic device sizes continue to shrink. In the past, an electronic device layout was large enough to accommodate unrestricted via layout. The unrestricted via layout provides a relaxed spacing between neighboring vias, which gives rise to a lower packing density. Today, with electronic device designs, and individual electronic device components such as vias, becoming increasingly smaller and smaller, individual components are required to be spaced closer for a tight packing density.
For example, to resolve minimum spacing between individual components, off-axis illumination with a combination of sub-resolution assist features has been used for 65 nm node hole imaging. When technology advances to 45 nm or less node, very strong off-axis illumination or immersion lithography at higher NA is required. Problems still arise, however, due to insufficient process margin for the manufacturing and the higher cost of the strong off-axis illumination.
Thus, there is a need to overcome these and other problems of the prior art and to provide an IC design layout and the method for laying out the IC design for randomly placing features in the presence of strong pitch restrictions.